The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2025

Filed:

Dec. 01, 2023
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Adithya Hrudhayan Krishnamurthy, Sunnyvale, CA (US);

Ish Chadha, San Jose, CA (US);

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/07 (2006.01); G06F 11/16 (2006.01);
U.S. Cl.
CPC ...
G06F 11/076 (2013.01); G06F 11/0745 (2013.01); G06F 11/0757 (2013.01); G06F 11/0772 (2013.01); G06F 11/1679 (2013.01);
Abstract

A receiver device includes detection logic, error counter logic, and threshold logic. The detection detects frame errors in data frames received by a transmitter device. The error counter logic increments a first value of an error count responsive to each error signal, indicative of a frame error in a data frame, received from the detection logic. The error counter logic reduces the first value to a second value (non-zero value) for the error count responsive to receiving a decrement signal and a period marker signal corresponding to a programmable period. The error counter logic resets the first value or the second value of the error count to zero responsive to receiving a reset signal. The threshold logic compares a current value of the error count with a threshold number of frame errors and output an interrupt responsive to the current value satisfying the threshold number of frame errors.


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