The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2025

Filed:

Nov. 15, 2019
Applicant:

Vermon S.a., Tours, FR;

Inventors:

Dominique Gross, Tours, FR;

Cyril Meynier, Tours, FR;

Nicolas Sénégond, Tours, FR;

Assignee:

VERMON S.A., Tours, FR;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B06B 1/02 (2006.01); B81B 3/00 (2006.01); B81C 1/00 (2006.01);
U.S. Cl.
CPC ...
B06B 1/0292 (2013.01); B81B 3/0086 (2013.01); B81C 1/00698 (2013.01); B81B 2201/0271 (2013.01); B81B 2203/0127 (2013.01); B81B 2203/0307 (2013.01); B81B 2203/0315 (2013.01); B81B 2203/04 (2013.01); B81C 2201/0125 (2013.01); B81C 2201/0132 (2013.01); B81C 2201/0178 (2013.01); B81C 2203/036 (2013.01);
Abstract

A capacitive micromachined ultrasonic transducer including a lower electrode, an upper electrode, and a membrane attached to the upper electrode and positioned between the lower electrode and the upper electrode. Anchors are connect to the membrane and the lower electrode such that a cavity is defined between the lower electrode and the membrane. One or more posts are positioned within the cavity, the posts partially buried within the membrane and extending towards the lower electrode. A method of producing a capacitive micromachined ultrasonic transducer includes forming an oxide growth layer on a device layer of undoped silicon and removing portions of the oxide growth layer to form anchors extending beyond the outer surface of the device layer and posts partially buried within post holes in the device layer and extending beyond the outer surface of the device layer.


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