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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12349586 B1

PDFFull Text
Date of Patent:
Jul. 01, 2025

Filed:

Jul. 19, 2021

Electronic display device having plurality of openings in common electrode overlapping transmission portions of blocking pattern, and method for manufacturing the same

Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

Moosoon Ko, Seoul, KR;

Yong-Je Jeon, Yongin-si, KR;

Sewan Son, Yongin-si, KR;

Jingoo Jung, Seongnam-si, KR;

Kyung Hyun Choi, Seoul, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:

Womble Bond Dickinson (US) LLP

Primary Examiner:

Matthew E Gordon

Int. Cl.
CPC ...
H10K 71/00 (2023.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10K 50/822 (2023.01); H10K 59/12 (2023.01); H10K 59/121 (2023.01); H10K 59/124 (2023.01); H10K 59/126 (2023.01); H10K 59/131 (2023.01); H10K 59/80 (2023.01); H10K 71/40 (2023.01);
U.S. Cl.
CPC ...
H10K 71/621 (2023.02); H10K 50/822 (2023.02); H10K 59/1213 (2023.02); H10K 59/124 (2023.02); H10K 59/126 (2023.02); H10K 59/131 (2023.02); H10K 59/80521 (2023.02); H10K 71/00 (2023.02); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10K 59/1201 (2023.02); H10K 71/421 (2023.02);
Abstract

An electronic device includes: a display panel including a display region including a first display region and a second display region having a higher transmittance than the first display region and an electronic module below the second display region of the display panel, wherein the display panel includes: a base layer; a plurality of first pixel electrodes on the base layer and in the first display region; a plurality of second pixel electrodes on the base layer and in the second display region; a common electrode on the plurality of first pixel electrodes and the plurality of second pixel electrodes and in which a plurality of openings are defined; and a blocking pattern spaced apart from the common electrode with the plurality of second pixel electrodes interposed therebetween and having a plurality of transmission portions overlapping the plurality of openings.

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