The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 01, 2025

Filed:

Apr. 22, 2024
Applicants:

Beijing Boe Display Technology Co., Ltd., Beijing, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Feng Li, Beijing, CN;

Yu Ma, Beijing, CN;

Yuqiong Chen, Beijing, CN;

Na Wen, Beijing, CN;

Qi Sang, Beijing, CN;

Yan Yan, Beijing, CN;

Jing Wang, Beijing, CN;

Weitao Chen, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 86/60 (2025.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); H10D 86/40 (2025.01);
U.S. Cl.
CPC ...
H10D 86/60 (2025.01); G02F 1/136286 (2013.01); G02F 1/1368 (2013.01); H10D 86/443 (2025.01);
Abstract

Disclosed are an array substrate and a display apparatus. The array substrate includes a base substrate; pixel circuits; gate lines; and pixel electrodes, where each pixel electrode includes a first end portion and a second end portion, intermediate portions connecting the first end portion and the second end portion, and a convex portion located on one side of the second end portion, the intermediate portions extend obliquely relative to both the first direction and the second direction, the convex portion extends in a direction at an obtuse angle to an extending direction of the intermediate portions, a slit between adjacent intermediate portions is a parallelogram, and an orthographic projection of the slit on the base substrate does not overlap with an orthographic projection of the pixel circuit on the base substrate and an orthographic projection of the gate line on the base substrate.


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