The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 01, 2025

Filed:

Jan. 25, 2022
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Heng Wu, Guilderland, NY (US);

Junli Wang, Slingerlands, NY (US);

Teresa J. Wu, Rexford, NY (US);

Tenko Yamashita, Schenectady, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/03 (2025.01); H01L 21/02 (2006.01); H01L 23/50 (2006.01); H01L 25/065 (2023.01); H10B 41/20 (2023.01); H10B 51/20 (2023.01); H10D 84/01 (2025.01);
U.S. Cl.
CPC ...
H10D 84/038 (2025.01); H01L 21/02532 (2013.01); H01L 23/50 (2013.01); H01L 25/0652 (2013.01); H10B 41/20 (2023.02); H10D 84/0167 (2025.01); H10D 84/0186 (2025.01); H10B 51/20 (2023.02);
Abstract

Embodiments of present invention provide a semiconductor device. The semiconductor device includes a silicon (Si) substrate containing a set of short channel field-effect-transistors (FETs); a germanium (Ge) layer on top of the Si substrate containing a set of long channel p-type FETs (PFETs); and an oxide semiconductor layer on top of the Ge layer containing a set of long channel n-type FETs (NFETs), wherein the set of short channel FETs, long channel PFETs, and long channel NFETs are interconnected through a set of far-back-end-of-line (FBEOL) layers.


Find Patent Forward Citations

Loading…