The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 01, 2025

Filed:

Jul. 07, 2021
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Yazhou Zhang, Shanghai, CN;

Jiandi Du, Shanghai, CN;

Hope Chiu, Shanghai, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); G11C 11/06 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H01L 25/10 (2006.01); H10B 41/27 (2023.01); H01L 23/00 (2006.01); H01L 25/18 (2023.01); H10B 80/00 (2023.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); G11C 11/06 (2013.01); H01L 23/31 (2013.01); H01L 23/5386 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H10B 41/27 (2023.02); H01L 24/48 (2013.01); H01L 25/18 (2013.01); H01L 2224/48147 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1052 (2013.01); H10B 80/00 (2023.02);
Abstract

A semiconductor memory device includes first memory dies stacked one upon another and electrically connected one to another by first bond wires, and covered with a first encapsulant. Second memory dies are disposed above the first memory dies, stacked one upon another and electrically connected one to another with second bond wires, and covered with a second encapsulant. A control die may be mounted on the top die in the second die stack. Vertical bond wires extend between the stacked die modules. A redistribution layer is formed over the top die stack and the control die to allow for electrical communication with the memory device. The memory device allows for stacking memory dies in a manner that allows for increased memory capacity without increasing the package form factor.


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