The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 01, 2025
Filed:
Mar. 14, 2022
High Tech Technology Limited, Hong Kong, HK;
Chik Wai (David) Ng, Hong Kong, HK;
Kwun Yuan (Godwin) Ho, Hong Kong, HK;
Ki Hin (Gary) Choi, Hong Kong, HK;
Tin Ho (Andy) Wu, Hong Kong, HK;
Wai Kit (Victor) So, Hong Kong, HK;
HIGH TECHNOLOGY LIMITED, Hong Kong, HK;
Abstract
An Integrated Circuit (IC) package has a ferrite-dielectric shield between planar transformer coils and a semiconductor chip. The shield blocks Electro-Magnetic Interference (EMI) generated by currents in transformer coils from reaching the semiconductor chip. Multiple layers of planar transformer coils serve as primary or secondary coils and can be connected together in series or parallel using center posts and coil extensions from outer coil windings to lead-frame risers that also have external package connectors such as pins or bonding balls. The center winding of an upper transformer coil connects to the semiconductor chip on a die attach pad through a center post that fits through an opening in the shield that is over the air core center of the transformer coil. Bonding wires connect pads on the semiconductor chip to lead-frame pads on lead-frame risers that end at external package connectors.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile