The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 01, 2025
Filed:
Jan. 02, 2024
Applicant:
Infineon Technologies Dresden Gmbh & Co. KG, Dresden, DE;
Inventors:
Assignee:
Infineon Technologies Dresden GmbH & Co. KG, Dresden, DE;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/265 (2006.01); H01L 21/266 (2006.01); H10D 18/00 (2025.01); H10D 30/01 (2025.01); H10D 30/65 (2025.01); H10D 62/17 (2025.01); H10D 64/66 (2025.01); H10D 84/00 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/60 (2025.01); H10F 77/20 (2025.01); H10F 77/60 (2025.01);
U.S. Cl.
CPC ...
H01L 21/265 (2013.01); H01L 21/2652 (2013.01); H01L 21/266 (2013.01); H10D 30/0281 (2025.01); H10D 30/65 (2025.01); H10D 84/013 (2025.01); H10D 84/038 (2025.01); H10D 62/393 (2025.01);
Abstract
A lateral high-voltage transistor includes a semiconductor substrate, a body region formed by dopant implantation in the semiconductor substrate, the body region having a lateral boundary, a dielectric layer arranged over the semiconductor substrate, and a structured gate layer arranged over the dielectric layer. The structured gate layer overlaps the body region in the semiconductor substrate in a zone between the lateral boundary of the body region and a gate edge of the structured gate layer. The lateral boundary of the body region is a boundary defined by dopant implantation.