The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 01, 2025

Filed:

Feb. 06, 2024
Applicant:

Lodestar Licensing Group Llc, Evanston, IL (US);

Inventors:

Robert Nasry Hasbun, San Jose, CA (US);

Dean D. Gans, Nampa, ID (US);

Sharookh Daruwalla, San Ramon, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/22 (2006.01); G06F 13/36 (2006.01); G11C 7/10 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G11C 7/22 (2013.01); G06F 13/36 (2013.01); G11C 7/10 (2013.01); G06F 13/1689 (2013.01);
Abstract

Methods, systems, and devices for a latency indication in a memory system or sub-system are described. An interface controller of a memory system may transmit an indication of a time delay (e.g., a wait signal) to a host in response to receiving an access command from the host. The interface controller may transmit such an indication when a latency associated with performing the access command is likely to be greater than a latency anticipated by the host. The interface controller may determine a time delay based on a status of buffer or a status of memory device, or both. The interface controller may use a pin designated and configured to transmit a command or control information to the host when transmitting a signal including an indication of a time delay. The interface controller may use a quantity, duration, or pattern of pulses to indicate a duration of a time delay.


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