The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 01, 2025

Filed:

Aug. 18, 2022
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventors:

Yuki Okamoto, Kanagawa, JP;

Tatsuya Onuki, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4097 (2006.01); G11C 11/4091 (2006.01); H10D 30/67 (2025.01); H10D 62/80 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10D 87/00 (2025.01);
U.S. Cl.
CPC ...
G11C 11/4097 (2013.01); G11C 11/4091 (2013.01); H10D 30/6734 (2025.01); H10D 30/6755 (2025.01); H10D 62/80 (2025.01); H10D 86/423 (2025.01); H10D 86/441 (2025.01); H10D 86/481 (2025.01); H10D 86/60 (2025.01); H10D 87/00 (2025.01);
Abstract

A novel memory device is provided. A first cell array including a plurality of memory cells and a second cell array including a plurality of memory cells are provided to overlap with each other. Two bit lines included in the first bit line pair are electrically connected to part of the memory cells included in the first cell array and to part of the memory cells included in the second cell array. Two bit lines included in the second bit line pair are electrically connected to part of the memory cells included in the first cell array and to part of the memory cells included in the second cell array. In the first cell array, one of the bit lines included in the second bit line pair includes a region overlapping with part of the first bit line pair. In the second cell array, the other of the bit lines included in the second bit line pair includes a region overlapping with part of the first bit line pair.


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