The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 01, 2025

Filed:

Oct. 09, 2023
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Paul Wielage, Waalre, NL;

Ayoub Rifai, Toulouse, FR;

Dominique Delbecq, Fonsorbes, FR;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); H03M 1/06 (2006.01); H03M 1/60 (2006.01); H03M 1/66 (2006.01);
U.S. Cl.
CPC ...
G06F 9/30145 (2013.01); G06F 9/30032 (2013.01); G06F 9/30098 (2013.01); H03M 1/066 (2013.01); H03M 1/66 (2013.01);
Abstract

A dynamic element matching system including sequential register groups, decode circuitry, and pointer control circuitry. Each register group includes at least two registers. The decode circuitry controls a state of each register group based on a level of a digital input signal, a relative position with respect to a begin pointer and an end pointer, and a corresponding one of multiple pseudo random probability values. The pointer control circuitry cyclically advances the end pointer among the register groups causing decode circuitry to add one or more register groups and enable a register within each added register group in response to the level of the digital input signal increasing, and also cyclically advances the begin pointer among the register groups causing the decode circuitry to remove one or more register groups and disable a register within each removed register group in response to the level of the digital input signal decreasing.


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