The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 01, 2025

Filed:

Aug. 21, 2023
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

Vadim Makhervaks, Bellevue, WA (US);

Aaron William Ogus, Woodinville, WA (US);

Jason David Adrian, Woodinville, WA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 9/455 (2018.01); G06F 12/02 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1673 (2013.01); G06F 9/45558 (2013.01); G06F 12/0284 (2013.01); G06F 13/4022 (2013.01); G06F 2009/45583 (2013.01); G06F 2213/0026 (2013.01);
Abstract

A server system is provided that includes one or more compute nodes that include at least one processor and a host memory device. The server system further includes a plurality of solid-state drive (SSD) devices, a local non-volatile memory express virtualization (LNV) device, and a non-transparent (NT) switch for a peripheral component interconnect express (PCIe) bus that interconnects the plurality of SSD devices and the LNV device to the at least one processor of each compute node. The LNV device is configured to virtualize hardware resources of the plurality of SSD devices. The plurality of SSD devices are configured to directly access data buffers of the host memory device. The NT switch is configured to hide the plurality of SSD devices such that the plurality of SSD devices are not visible to the at least one processor of each compute node.


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