The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 01, 2025

Filed:

Apr. 26, 2023
Applicant:

General Electric Company, Schenectady, NY (US);

Inventors:

Kum Kang Huh, Niskayuna, NY (US);

Hridya Ittamveettil, Bengaluru, IN;

Luis J. Garces, Niskayuna, NY (US);

Rajib Datta, Niskayuna, NY (US);

Di Pan, Schenectady, NY (US);

Yukai Wang, Schenectady, NY (US);

Assignee:

General Electric Company, Evendale, OH (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); B64D 41/00 (2006.01); G06F 1/30 (2006.01); H02M 1/00 (2006.01); H02M 7/797 (2006.01); G06F 1/3203 (2019.01);
U.S. Cl.
CPC ...
G06F 1/30 (2013.01); B64D 41/00 (2013.01); H02M 1/0043 (2021.05); H02M 7/797 (2013.01); G06F 1/3203 (2013.01);
Abstract

A multilevel power converter includes a plurality of switches, a first DC link capacitor, a second DC link capacitor, and one or more processors configured to: generate, for a duty cycle of the multilevel power converter, a pulse width modulated pulse pattern in accordance with a reduced common mode voltage scheme; modify the pulse width modulated pulse pattern to render a modified pulse pattern; and cause the plurality of switches to implement the duty cycle based at least in part on the modified pulse pattern to render a common mode voltage pulse to balance voltages at the first DC link capacitor and the second DC link capacitor.


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