The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 24, 2025

Filed:

Jan. 19, 2024
Applicant:

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Mei Li, Beijing, CN;

Tian Dong, Beijing, CN;

Li Wang, Beijing, CN;

Guangliang Shang, Beijing, CN;

Can Zheng, Beijing, CN;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10K 59/131 (2023.01); G09G 3/3233 (2016.01); G09G 3/3266 (2016.01); G09G 3/3275 (2016.01); H10K 59/121 (2023.01); G06F 3/00 (2006.01); G06F 3/033 (2013.01); H10K 102/00 (2023.01);
U.S. Cl.
CPC ...
H10K 59/131 (2023.02); G09G 3/3233 (2013.01); G09G 3/3266 (2013.01); G09G 3/3275 (2013.01); H10K 59/121 (2023.02); G06F 3/00 (2013.01); G06F 3/033 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2320/0214 (2013.01); G09G 2320/0247 (2013.01); G09G 2330/02 (2013.01); G09G 2330/021 (2013.01); H10K 2102/302 (2023.02);
Abstract

A display panel and a display device are provided. The display panel includes a pixel unit, a data line, and a connection element, the connection element includes a shielding portion, the shielding portion and the data line extend in the same direction; the pixel circuit includes a driving transistor and a first transistor, a first electrode of the first transistor is connected with the data line, a first electrode of the driving transistor is connected with a second electrode of the first transistor, the display panel further includes a semiconductor pattern and a fourth conductive pattern layer, the fourth conductive pattern layer is located on a side of the semiconductor pattern away from a base substrate, the data line and the shielding portion are located in the fourth conductive pattern, the data line includes two adjacent data lines, the shielding portion is located between the two adjacent data lines.


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