The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 24, 2025

Filed:

Jul. 26, 2021
Applicant:

Lextar Electronics Corporation, Hsinchu, TW;

Inventor:

Shiou-Yi Kuo, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10H 20/831 (2025.01); H10H 20/85 (2025.01); H10H 20/857 (2025.01);
U.S. Cl.
CPC ...
H10H 20/8312 (2025.01); H10H 20/8506 (2025.01); H10H 20/857 (2025.01);
Abstract

A semiconductor chip comprises a semiconductor stack and a passivation layer. The semiconductor stack comprises a top surface, a bottom surface opposite to the top surface, and a plurality of sidewalls between the top surface and the bottom surface. The passivation layer conformally covers the top surface and the sidewalls of the semiconductor stack. When viewing from the bottom surface, a plan-view contour of the semiconductor stack comprises a plurality of edges and corners. Each of the corners is defined by two adjacent edges. A plan-view contour of the passivation layer surrounding the plan-view contour of the semiconductor stack comprises a protruding portion adjacent to one of the corners and the protruding portion protrudes outwards from the plan-view contour of the passivation layer.


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