The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 24, 2025

Filed:

Dec. 19, 2022
Applicant:

Auo Corporation, Hsinchu, TW;

Inventors:

Ssu-Hui Lu, Hsinchu, TW;

Chang-Hung Li, Hsinchu, TW;

Kuo-Yu Huang, Hsinchu, TW;

Maw-Song Chen, Hsinchu, TW;

Assignee:

AUO Corporation, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 86/01 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01);
U.S. Cl.
CPC ...
H10D 86/60 (2025.01); H10D 30/0321 (2025.01); H10D 30/6715 (2025.01); H10D 30/6723 (2025.01); H10D 30/6734 (2025.01); H10D 30/6745 (2025.01); H10D 30/6757 (2025.01); H10D 86/0221 (2025.01); H10D 86/0231 (2025.01); H10D 86/421 (2025.01);
Abstract

A thin film transistor includes a bottom gate, a semiconductor layer, a top gate, a first auxiliary conductive pattern, a source, and a drain. The semiconductor layer includes a first semiconductor region, a second semiconductor region, a first heavily doped region, a second heavily doped region, a third heavily doped region, a first lightly doped region, a second lightly doped region, and a third lightly doped region. The first heavily doped region and the second heavily doped region are respectively located on two sides of the first semiconductor region. Two ends of the second semiconductor region are directly connected to the third heavily doped region and the third lightly doped region, respectively. The top gate is electrically connected to the bottom gate. The source and the drain are respectively electrically connected to the third heavily doped region and the second heavily doped region of the semiconductor layer.


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