The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 24, 2025
Filed:
Sep. 29, 2023
Applicant:
SK Hynix Inc., Icheon-si Gyeonggi-do, KR;
Inventor:
Young Jae An, Icheon-si Gyeonggi-do, KR;
Assignee:
SK hynix Inc., Icheon-si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/081 (2006.01); H03K 5/156 (2006.01); H03L 7/085 (2006.01); H04L 7/00 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0816 (2013.01); H03K 5/1565 (2013.01); H03L 7/085 (2013.01); H04L 7/0037 (2013.01);
Abstract
A clock generation circuit includes a delay-locked circuit and a duty correction circuit. The delay-locked circuit generates a delay clock signal by delaying an input clock signal and update the delay time of the input clock signal. The duty correction circuit generates a first phase clock signal and a second phase clock signal by delaying the delay clock signal, and updates the delay time of the delay clock signal. The duty correction circuit can prevent or mitigate the delay time of the input clock signal and the delay time of the delay clock signal from being updated simultaneously.