The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 24, 2025
Filed:
Nov. 22, 2022
Tower Semiconductor Ltd., Migdal Haemek, IL;
Efraim Aharoni, Haifa, IL;
Avi Parvin, Netania, IL;
Roda Kanawati, Irvine, CA (US);
Allon Parag, Ramat Yishai, IL;
Einat Arad Ophir, Yuvalim, IL;
TOWER SEMICONDUCTOR LTD., Migdal Haemek, IL;
Abstract
For example, a multi voltage-domain Electro Static Discharge (ESD) power clamp may include a plurality of pins; and an ESD array including a cascaded plurality of ESD power clamps. For example, the ESD array may include a plurality of ESD array portions configured to protect a respective plurality of voltage domains from ESD. For example, the ESD array may be configured to connect the plurality of ESD array portions between a respective plurality of pin pairs from the plurality of pins. For example, an ESD array portion corresponding to a voltage domain may include one or more ESD power clamps of the cascaded plurality of ESD power clamps. For example, the ESD array portion may be configured to protect a voltage range of the voltage domain.