The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 24, 2025

Filed:

Sep. 29, 2022
Applicant:

Tdk—micronas Gmbh, Freiburg, DE;

Inventors:

Paolo Marozzi, Freiburg, DE;

Ingo Freund, Freiburg, DE;

Assignee:

TDK—Micronas GmbH, Freiburg, DE;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); G01D 5/14 (2006.01); G01R 33/00 (2006.01); G01R 33/07 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 25/16 (2023.01);
U.S. Cl.
CPC ...
H01L 25/16 (2013.01); G01D 5/145 (2013.01); G01R 33/0094 (2013.01); G01R 33/072 (2013.01); H01L 21/4825 (2013.01); H01L 23/49575 (2013.01); H01L 23/49589 (2013.01); H01L 24/48 (2013.01); H01L 2224/48175 (2013.01); H01L 2924/19041 (2013.01);
Abstract

A dual die integrated circuit (IC) system () in an integrated circuit (IC) package () with two separate supply domains is provided comprising a first die (); a second die (); a lead frame () having a first ground pin (GND), a first supply voltage (Vsup), a second ground pin (GND), and a second supply voltage (Vsup), wherein the first die () is connected to the first ground pin (GND) and to the first supply voltage (Vsup) and wherein the second die () is connected to the second ground pin (GND) and to the second supply voltage (Vsup); and at least one capacitive element () coupled between the first ground pin (GND) and the second ground pin (GND) and coupled between the first supply voltage (Vsup) and the second supply voltage (Vsup).


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