The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 24, 2025

Filed:

Apr. 10, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Seunghwan Hong, Suwon-si, KR;

Jang-Woo Ryu, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/40 (2006.01); G06F 1/12 (2006.01); G11C 11/4076 (2006.01); G11C 11/408 (2006.01); H03K 3/037 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4076 (2013.01); G06F 1/12 (2013.01); G11C 11/4087 (2013.01); H03K 3/037 (2013.01); H03K 19/20 (2013.01);
Abstract

A semiconductor device includes a chip select signal flip-flop configured to: latch a chip select signal in-sync with a first propagation clock signal, and output a first chip select enable signal, and latch the chip select signal in-sync with a second propagation clock signal having a phase opposite to a phase of the first propagation clock signal, and output a second chip select enable signal; and a clock control circuit configured to generate the first propagation clock signal and the second propagation clock signal based on a clock signal, and selectively output one of the first propagation clock signal and the second propagation clock signal based on an enable level of the first chip select enable signal and an enable level of the second chip select enable signal.


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