The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 24, 2025

Filed:

Mar. 13, 2024
Applicant:

Auo Corporation, Hsinchu, TW;

Inventors:

Kuo-Wei Ho, Hsinchu, TW;

Sheng-Yen Cheng, Hsinchu, TW;

Yueh-Hung Chung, Hsinchu, TW;

Ya-Ling Hsu, Hsinchu, TW;

Assignee:

AUO Corporation, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 3/32 (2016.01); H01L 25/075 (2006.01); H01L 25/16 (2023.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10H 20/857 (2025.01);
U.S. Cl.
CPC ...
G09G 3/32 (2013.01); H01L 25/0753 (2013.01); H01L 25/167 (2013.01); H10D 86/441 (2025.01); H10D 86/60 (2025.01); H10H 20/857 (2025.01); G09G 2310/0267 (2013.01); G09G 2310/0275 (2013.01);
Abstract

A pixel array substrate includes a substrate, a gate driver circuit, a first conductive pattern, a first dielectric layer, a second conductive pattern, a second dielectric layer, and a third conductive pattern. The first conductive pattern includes a first branch clock signal line which is electrically connected to the gate driver circuit. The first conductive pattern is located between the substrate and the first dielectric layer. The second conductive pattern is located between the first dielectric layer and the second dielectric layer and includes a shielding structure. The third conductive pattern is located on the second dielectric layer and includes a first clock signal line and a data line. The first branch clock signal line electrically connects the first clock signal line to the gate driver circuit and intersects the data line. The shielding structure is located between the data line and the first branch clock signal line.


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