The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 24, 2025
Filed:
Feb. 07, 2024
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Martin Langhammer, Alderbury, GB;
Dongdong Chen, San Jose, CA (US);
Jason R. Bergendahl, Cupertino, CA (US);
Assignee:
Altera Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 7/483 (2006.01); G06F 7/50 (2006.01); G06F 7/523 (2006.01); G06F 7/556 (2006.01); G06F 30/34 (2020.01); G06F 30/343 (2020.01); G06F 30/38 (2020.01); G06N 20/00 (2019.01); H03K 19/177 (2020.01); H03K 19/17748 (2020.01); H03M 7/24 (2006.01);
U.S. Cl.
CPC ...
G06F 9/30101 (2013.01); G06F 7/50 (2013.01); G06F 7/523 (2013.01); G06F 7/556 (2013.01); G06F 9/30105 (2013.01); G06F 30/34 (2020.01); G06F 30/343 (2020.01); G06F 30/38 (2020.01); G06N 20/00 (2019.01); H03K 19/177 (2013.01); H03K 19/17748 (2013.01); H03M 7/24 (2013.01); G06F 7/483 (2013.01);
Abstract
The present disclosure describes a digital signal processing (DSP) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.