The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 24, 2025

Filed:

Mar. 03, 2023
Applicant:

The Mitre Corporation, McLean, VA (US);

Inventors:

Roshan K. Thomas, Centreville, VA (US);

Gananand G. Kini, Ashburn, VA (US);

Assignee:

The MITRE Corporation, McLean, VA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 8/656 (2018.01); G05B 19/418 (2006.01); G05B 23/02 (2006.01); G06F 8/61 (2018.01);
U.S. Cl.
CPC ...
G06F 8/656 (2018.02); G05B 19/418 (2013.01); G05B 23/0235 (2013.01); G06F 8/61 (2013.01);
Abstract

Described herein are systems and methods for performing real-time binary analysis of code running in programmable logic controllers, and specifically to systems and methods for generating patches, testing patches, and implementing patches on programmable logic controllers while the controller is operating is provided. In one or more examples, a profile of the physical operation controlled by the PLC and the broader system can be generated. In one or more examples, once a profile has been generated, the system and methods described herein can capture data images that provide information regarding the operation of the system as well as the PLC. Based on the received data images, and the generated profile, the system can detect anomalies and/or safety constraint violations in the operation of the system that can be rectified or mitigated through patching (i.e., modification of the datasets or binary code used by the PLC).


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