The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 24, 2025

Filed:

Sep. 18, 2023
Applicant:

Dell Products, L.p., Round Rock, TX (US);

Inventors:

Akkiah Choudary Maddukuri, Austin, TX (US);

Timothy M. Lambert, Austin, TX (US);

Elie Antoun Jreij, Pflugerville, TX (US);

Bhavesh Govindbhai Patel, Austin, TX (US);

Mukund P. Khatri, Austin, TX (US);

Assignee:

Dell Products, L.P., Round Rock, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/26 (2006.01); G06F 1/28 (2006.01); G06F 9/48 (2006.01); G06F 11/30 (2006.01);
U.S. Cl.
CPC ...
G06F 1/26 (2013.01); G06F 9/4893 (2013.01); G06F 1/28 (2013.01); G06F 11/3062 (2013.01);
Abstract

Embodiments of systems and methods for power throttling of High Performance Computing (HPC) components are described. In some embodiments, an HPC platform may include: a system Baseboard Management Controller (BMC), and an accelerator tray comprising a tray BMC coupled to a plurality of managed subsystems and to the system BMC, where the system BMC is configured to: in response to a power excursion event, instruct the tray BMC to throttle a first managed subsystem by a first amount and to throttle a second managed subsystem by a second amount.


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