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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12336388 B1

PDFFull Text
Date of Patent:
Jun. 17, 2025

Filed:

Jun. 30, 2022

Thin film transistor, method for fabricating the thin film transistor, thin film transistor array substrate, and method for fabricating the thin film transistor array substrate

Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

Jong Chan Lee, Suwon-si, KR;

Jung Eun Hong, Seoul, KR;

Jin Taek Kim, Yongin-si, KR;

Hyun Kim, Seoul, KR;

Jeong Su Park, Asan-si, KR;

Woong Hee Jeong, Seoul, KR;

Assignee:

SAMSUNG DISPLAY CO., LTD., Yongin-si, KR;

Attorney:

KILE PARK REED & HOUTTEMAN PLLC

Primary Examiner:

Timor Karimy

Int. Cl.
CPC ...
H10K 59/121 (2023.01); H10D 30/67 (2025.01); H10D 86/60 (2025.01); H10K 59/126 (2023.01); H10K 59/131 (2023.01); H10K 71/00 (2023.01); H10D 86/40 (2025.01); H10K 59/12 (2023.01);
U.S. Cl.
CPC ...
H10K 59/1213 (2023.02); H10K 59/1216 (2023.02); H10K 59/126 (2023.02); H10K 59/131 (2023.02); H10K 71/00 (2023.02); H10D 30/6723 (2025.01); H10D 30/6755 (2025.01); H10D 86/423 (2025.01); H10D 86/441 (2025.01); H10D 86/481 (2025.01); H10D 86/60 (2025.01); H10K 59/1201 (2023.02);
Abstract

A method for fabricating a thin film transistor comprises disposing a semiconductor layer including a channel area, and a first and second electrode areas, disposing a gate insulating layer covering the semiconductor layer, disposing a diffusion barrier layer covering the gate insulating layer, disposing first and second electrode holes corresponding to the first and second electrode areas, and disposing a gate electrode overlapping the channel area, first and second electrodes electrically connected to the first and second electrode areas through the first and second electrode holes. The disposing of the first electrode hole, and the second electrode hole includes patterning the diffusion layer with a patterning mask disposed on the diffusion barrier layer. The disposing of the gate electrode and the first and second electrodes may include disposing a conductive material layer covering the diffusion barrier layer, and patterning the conductive material layer.

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