The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2025

Filed:

Feb. 20, 2024
Applicant:

Sony Semiconductor Solutions Corporation, Kanagawa, JP;

Inventors:

Hideto Hashiguchi, Kanagawa, JP;

Reijiroh Shohji, Kanagawa, JP;

Hiroshi Horikoshi, Kanagawa, JP;

Ikue Mitsuhashi, Kanagawa, JP;

Tadashi Iijima, Kanagawa, JP;

Takatoshi Kameshima, Kanagawa, JP;

Minoru Ishida, Kanagawa, JP;

Masaki Haneda, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10F 39/00 (2025.01); H10F 39/12 (2025.01); H10F 39/18 (2025.01);
U.S. Cl.
CPC ...
H10F 39/811 (2025.01); H10F 39/182 (2025.01); H10F 39/199 (2025.01); H10F 39/8023 (2025.01); H10F 39/8037 (2025.01); H10F 39/809 (2025.01);
Abstract

To provide a solid-state imaging device and an electronic apparatus with further improved performance. A solid-state imaging device including: a first substrate on which a pixel unit is formed, and a first semiconductor substrate and a first multi-layered wiring layer are stacked; a second substrate on which a circuit having a predetermined function is formed, and a second semiconductor substrate and a second multi-layered wiring layer are stacked; and a third substrate on which a circuit having a predetermined function is formed, and a third semiconductor substrate and a third multi-layered wiring layer are stacked. The first substrate, the second substrate, and the third substrate are stacked in this order. The pixel unit has pixels arranged thereon. The first substrate and the second substrate are bonded together in a manner that the first multi-layered wiring layer and the second semiconductor substrate are opposed to each other. A first coupling structure for electrically coupling a circuit of the first substrate and the circuit of the second substrate to each other does not include a coupling structure formed from the first substrate as a base over bonding surfaces of the first substrate and the second substrate. Alternatively, the first coupling structure does not exist.


Find Patent Forward Citations

Loading…