The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2025

Filed:

Sep. 01, 2023
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Sadia Arefin Khan, Dallas, TX (US);

Anant Shankar Kamath, Bengaluru, IN;

Martin Staebler, Freising, DE;

Vikas Kumar Thawani, Bengaluru, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04L 25/02 (2006.01); H02K 11/33 (2016.01); H02P 27/08 (2006.01); H03K 19/003 (2006.01); H03K 19/0175 (2006.01);
U.S. Cl.
CPC ...
H04L 25/0266 (2013.01); H02K 11/33 (2016.01); H02P 27/08 (2013.01); H03K 19/00323 (2013.01); H03K 19/017509 (2013.01); H03K 19/017545 (2013.01);
Abstract

A multi-channel digital isolator includes a digital isolator and an interlock circuit. The isolator includes a transmitter having a transmitter output, a receiver having a receiver input and a receiver output, an isolation barrier coupled between the transmitter output and the receiver input, and an output buffer having a buffer input and configured to output an isolated signal. The transmitter is configured to transmit an input signal across the isolation barrier. The interlock circuit has an interlock input coupled to the receiver output and an interlock output coupled to the buffer input. The interlock module is configured to prevent overlapping active states between the first isolated signal and a complementary isolated signal. In some implementations, the digital isolator also includes a dead-time insertion circuit.


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