The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 17, 2025
Filed:
Jan. 05, 2021
Sumitomo Electric Industries, Ltd., Osaka, JP;
Tatsuya Hashinaga, Osaka, JP;
Yutaka Moriyama, Osaka, JP;
SUMITOMO ELECTRIC INDUSTRIES, LTD., Osaka, JP;
Abstract
A high frequency amplifier includes an asymmetric Doherty amplifier configured to amplify a high frequency signal having a wavelength λ, the high frequency signal being input, and the asymmetric Doherty amplifier including a carrier amplifier and a peak amplifier, the peak amplifier being configured to start an amplifying operation when an output of the carrier amplifier reaches a saturation region and having a saturation output different from a saturation output of the carrier amplifier, a driver amplifier configured to drive the asymmetric Doherty amplifier, a branch circuit configured to branch the high frequency signal amplified by the driver amplifier into an input path on a peak amplifier side and an input path on a carrier amplifier side, a phase adjustment circuit configured to delay either a phase of a signal input to the peak amplifier or a phase of a signal input to the carrier amplifier, the phase adjustment circuit being provided on either the input path on the peak amplifier side or the input path on the carrier amplifier, a first substrate on which the carrier amplifier and the peak amplifier are mounted, and a second substrate on which the driver amplifier, the branch circuit, and the phase adjustment circuit are mounted. An input terminal of the driver amplifier and an input terminal of the carrier amplifier are disposed at positions where the input terminal of the driver amplifier and the input terminal of the carrier amplifier project to each other when the second substrate is stacked on the first substrate. An electrical length from the input terminal of the driver amplifier to an output terminal of the carrier amplifier is set to a phase of (2n+1)×π, where n is an integer greater than or equal to 0.