The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2025

Filed:

Sep. 30, 2022
Applicant:

Fuji Electric Co., Ltd., Kanagawa, JP;

Inventors:

Hiromu Takubo, Tokyo, JP;

Ryoga Kiguchi, Tokyo, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 1/08 (2006.01); H02M 1/38 (2007.01); H03K 17/16 (2006.01); H03K 17/687 (2006.01); H02M 7/537 (2006.01);
U.S. Cl.
CPC ...
H02M 1/08 (2013.01); H02M 1/385 (2021.05); H03K 17/161 (2013.01); H03K 17/687 (2013.01); H02M 7/537 (2013.01);
Abstract

According to the present disclosure, the deterioration of SiC-MOSFETs is suppressed. A drive device switches between a first SiC-MOSFET and a second SiC-MOSFET that are connected in series, with a dead time where the first SiC-MOSFET and the second SiC-MOSFET are commanded to be OFF being provided in between. This drive device includes: a first drive circuit configured to set the gate voltage of the first SiC-MOSFET, during the dead time, to a first middle voltage that is higher than a first negative power supply voltage and lower than a first threshold voltage for the first SiC-MOSFET; and a second drive circuit configured to set the gate voltage of the second SiC-MOSFET, during the dead time, to a second middle voltage that is higher than a second negative power supply voltage and lower than a second threshold voltage for the second SiC-MOSFET.


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