The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2025

Filed:

Oct. 26, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventor:

Hyun Mog Park, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2023.01); H10B 41/27 (2023.01); H10B 41/30 (2023.01); H10B 41/40 (2023.01); H10B 43/27 (2023.01); H10B 43/30 (2023.01); H10B 43/40 (2023.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H01L 24/08 (2013.01); H01L 24/89 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H10B 41/27 (2023.02); H10B 41/30 (2023.02); H10B 41/40 (2023.02); H10B 43/27 (2023.02); H10B 43/30 (2023.02); H10B 43/40 (2023.02); H01L 24/05 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80001 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06565 (2013.01);
Abstract

A semiconductor device includes a first substrate structure and a second substrate structure. The first substrate structure includes a base substrate, circuit elements disposed on the base substrate, a first substrate disposed on the circuit elements, first memory cells disposed on the first substrate and electrically connected to the circuit elements, first bit lines disposed on the first memory cells and connected to the first memory cells, and first bonding pads disposed on the first bit lines to be connected to the first bit lines, respectively. The second substrate structure is connected to the first substrate structure on the first substrate structure, and includes a second substrate, second memory cells disposed on the second substrate, second bit lines disposed on the second memory cells and connected to the second memory cells, and second bonding pads disposed on the second bit lines to be connected to the second bit lines, respectively. The first substrate structure and the second substrate structure are connected to each other by bonding the first bonding pads to the second bonding pads, and the first bonding pads and second bonding pads are vertically between the first bit lines and the second bit lines, without the first substrate or second substrate disposed vertically between the first bit lines and the second bit lines.


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