The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 17, 2025
Filed:
Mar. 23, 2023
Denso Corporation, Kariya, JP;
Toyota Jidosha Kabushiki Kaisha, Toyota, JP;
Mirise Technologies Corporation, Nisshin, JP;
National University Corporation Tokai National Higher Education and Research System, Nagoya, JP;
Hamamatsu Photonics K.k., Hamamatsu, JP;
Shosuke Nakabayashi, Nisshin, JP;
Masatake Nagaya, Nisshin, JP;
Chiaki Sasaoka, Nagoya, JP;
Shoichi Onda, Nagoya, JP;
Jun Kojima, Nagoya, JP;
Daisuke Kawaguchi, Hamamatsu, JP;
Ryuji Sugiura, Hamamatsu, JP;
Toshiki Yui, Hamamatsu, JP;
Keisuke Hara, Hamamatsu, JP;
Tomomi Aratani, Hamamatsu, JP;
DENSO CORPORATION, Kariya, JP;
TOYOTA JIDOSHA KABUSHIKI KAISHA, Toyota, JP;
MIRISE Technologies Corporation, Nisshin, JP;
National University Corporation Tokai National Higher Education and Research System, Nagoya, JP;
HAMAMATSU PHOTONICS K.K., Hamamatsu, JP;
Abstract
A manufacturing method of a semiconductor device, includes: forming a gas vent recess in a first surface of a compound semiconductor substrate, which includes a plurality of device regions adjacent to the first surface, along an interface between the plurality of device regions; forming an altered layer inside the compound semiconductor substrate to extend along the first surface at a depth corresponding to a range of a depth of the gas vent recess by applying a laser beam; dividing the compound semiconductor substrate at the altered layer into a first part including the first surface and a second part including a second surface of the compound semiconductor substrate opposite to the first surface; and forming a metal film to cover a divided surface of the first part while exposing the gas vent recess.