The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2025

Filed:

Sep. 12, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

YongHyun An, Suwon-si, KR;

Hae Young Chung, Suwon-si, KR;

Soyeong Shin, Suwon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 7/14 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1084 (2013.01); G11C 7/1012 (2013.01); G11C 7/14 (2013.01); G11C 2207/2254 (2013.01);
Abstract

A memory device includes a memory cell array and an input/output circuit. The input/output circuit is configured to: (i) generate second data in response to sampling first data by comparing the first data against a reference voltage, (ii) generate an offset calibration code corresponding to a first input offset of the input/output circuit based on the second data, prior to receiving a mode register code, (iii) change a gain of an input buffer corresponding to the mode register code after receiving the mode register code, and (iv) calibrate a second input offset corresponding to the changed gain of the input buffer by adjusting a current amount applied to a current element electrically connected to an input terminal of the input buffer based on the offset calibration code and the mode register code. Control logic may also be used to provide the mode register code, which includes gain information associated with the input/output circuit, to the input/output circuit.


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