The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2025

Filed:

Mar. 25, 2021
Applicant:

Intel Ndtm Us Llc, Santa Clara, CA (US);

Inventors:

Ali Khakifirooz, Brookline, MA (US);

Pranav Kalavade, San Jose, CA (US);

Shantanu Rajwade, Santa Clara, CA (US);

Tarek Ahmed Ameen Beshari, Santa Clara, CA (US);

Assignee:

SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G06F 3/06 (2006.01); G11C 16/10 (2006.01); G11C 16/24 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 16/0483 (2013.01); G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); G11C 16/3459 (2013.01);
Abstract

Systems, apparatuses and methods may provide for technology that boosts strings of a plurality of NAND sub-blocks to a pass voltage, deboosts a first subset of the boosted strings based on data associated with the plurality of NAND sub-blocks, and simultaneously programs the first subset while a second subset of the boosted strings remain at the pass voltage. In one example, to boost the strings of the NAND sub-blocks, the technology applies the pass voltage to selected and unselected wordlines that are connected to the NAND sub-blocks while selected and unselected strings are disconnected from a bitline that receives the data associated with the NAND sub-blocks.


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