The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 17, 2025
Filed:
Mar. 05, 2024
Apple Inc., Cupertino, CA (US);
Hyunwoo Nho, Palo Alto, CA (US);
Jie Won Ryu, San Jose, CA (US);
Patrick R Cruce, Campbell, CA (US);
Yao Shi, Sunnyvale, CA (US);
Nicolas Le Dortz, Palo Alto, CA (US);
Wei Xiong, Mountain View, CA (US);
Hyunsoo Kim, San Diego, CA (US);
Wei H Yao, Saratoga, CA (US);
Sun-Il Chang, San Jose, CA (US);
Kingsuk Brahma, Mountain View, CA (US);
Ionut A Mirel, Cupertino, CA (US);
Mahesh B Chappalli, San Jose, CA (US);
Ruicong Chen, San Jose, CA (US);
Apple Inc., Cupertino, CA (US);
Abstract
Embodiments herein provide various apparatuses and techniques to efficiently mitigate front-of-screen (FoS) artifacts that may occur due to voltage fluctuations due to alternating current (AC) or direct current (DC) mechanisms that may occur in a variety of pixel types. In one embodiment, emission profile awareness circuitry may be implemented to mitigate for FoS artifacts due to DC mechanisms. Two-dimensional (2D) digital compensation circuitry may address the DC portion of the voltage fluctuations by accounting for an emission profile applied to content displayed on an electronic display. In some embodiments, the 2D digital compensation circuitry may compensate for the AC portion of the voltage fluctuations by duplicating the AC voltage fluctuations via voltage error subtraction circuitry and voltage error accumulation circuitry.