The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2025

Filed:

Sep. 27, 2023
Applicant:

Lg Display Co., Ltd., Seoul, KR;

Inventors:

Soon Dong Cho, Paju-si, KR;

Jae Won Han, Paju-si, KR;

Jung Jae Kim, Paju-si, KR;

Min Gyu Park, Paju-si, KR;

Sang Uk Lee, Paju-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 3/20 (2006.01); G09G 3/3233 (2016.01); H03K 5/13 (2014.01);
U.S. Cl.
CPC ...
G09G 3/2096 (2013.01); G09G 3/3233 (2013.01); H03K 5/13 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/08 (2013.01);
Abstract

The present disclosure relates to a clock generator and a display device including the same. The clock generator includes a first clock generation circuit configured to output a clock, data, and a timing control signal; a first wiring through which the clock is serially transmitted; a second wiring through which the data is serially transmitted; a third wiring through which a pulse of the timing control signal is serially transmitted; a second clock generation circuit connected to the first clock generation circuit through the first wiring, the second wiring, and the third wiring and configured to generate pre-clocks in which phases are sequentially shifted based on the data and the clock; and a clock adjustment circuit configured to receive the pulse of the timing control signal and the pre-clock and output an output clock.


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