The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2025

Filed:

Apr. 10, 2024
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Borna J. Obradovic, Leander, TX (US);

Titash Rakshit, Austin, TX (US);

Mark S. Rodder, Dallas, TX (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06N 3/065 (2023.01); H10B 41/30 (2023.01); H10D 30/01 (2025.01); H10D 30/68 (2025.01); H10D 30/83 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
G06N 3/065 (2023.01); H10B 41/30 (2023.02); H10D 30/0411 (2025.01); H10D 30/681 (2025.01); H10D 30/6891 (2025.01); H10D 30/831 (2025.01); H10D 64/035 (2025.01);
Abstract

A neuromorphic device for the analog computation of a linear combination of input signals, for use, for example, in an artificial neuron. The neuromorphic device provides non-volatile programming of the weights, and fast evaluation and programming, and is suitable for fabrication at high density as part of a plurality of neuromorphic devices. The neuromorphic device is implemented as a vertical stack of flash-like cells with a common control gate contact and individually contacted source-drain (SD) regions. The vertical stacking of the cells enables efficient use of layout resources.


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