The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 17, 2025
Filed:
Apr. 07, 2023
Qualcomm Incorporated, San Diego, CA (US);
Srikar Karnam Venkat Naga, Bangalore, IN;
Vandit Chauhan, Hyderabad, IN;
Venkata Naga Satya Srinivas Nudurupati, Hyderabad, IN;
Karimulla Syed, Bangalore, IN;
Rohit Singh, Hyderabad, IN;
Virat Deepak, San Diego, CA (US);
Satyaki Mukherjee, Bangalore, IN;
Ashok Kumar Immadi, Hyderabad, IN;
Ronald Alton, Oceanside, CA (US);
QUALCOMM Incorporated, San Diego, CA (US);
Abstract
A system for performing peak current mitigation in an application programming subsystem (APSS) dynamically performs mitigation based at least in part on power rail voltage and leakage current obtained at boot time. The voltage and leakage current obtained at boot time are used to estimate peak current. A map that is generated prior to boot time maps estimated peak current to throttling level and dictates different levels of throttling to be performed for different ranges of estimated peak current. At boot time, the map is used to map the estimated peak current to a level of throttling to be applied. If conditions at run time indicate that peak current is occurring or is likely to occur soon, the mapped level of throttling is applied to mitigate the peak current.