The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 17, 2025
Filed:
Oct. 22, 2021
Arizona Board of Regents on Behalf of Arizona State University, Scottsdale, AZ (US);
Arizona Board of Regents on Behalf of the University of Arizona, Tucson, AZ (US);
Board of Regents, the University of Texas System, Austin, TX (US);
Carnegie Mellon University, Pittsburgh, PA (US);
Umit Ogras, Tempe, AZ (US);
Radu Marculescu, Austin, TX (US);
Ali Akoglu, Tucson, AZ (US);
Chaitali Chakrabarti, Tempe, AZ (US);
Daniel Bliss, Phoenix, AZ (US);
Samet Egemen Arda, Chandler, AZ (US);
Anderson Sartor, La Jolla, CA (US);
Nirmal Kumbhare, Tucson, AZ (US);
Anish Krishnakumar, Madison, WI (US);
Joshua Mack, Tucson, AZ (US);
Ahmet Goksoy, Madison, WI (US);
Sumit Mandal, Madison, WI (US);
ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY, Scottsdale, AZ (US);
ARIZONA BOARD OF REGENTS ON BEHALF OF THE UNIVERSITY OF ARIZONA, Tucson, AZ (US);
BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM, Austin, TX (US);
CARNEGIE MELLON UNIVERSITY, Pittsburgh, PA (US);
Abstract
Hierarchical and lightweight imitation learning (IL) for power management of embedded systems-on-chip (SoCs), also referred to herein as HiLITE, is provided. Modern SoCs use dynamic power management (DPM) techniques to improve energy efficiency. However, existing techniques are unable to efficiently adapt the runtime decisions considering multiple objectives (e.g., energy and real-time requirements) simultaneously on heterogeneous platforms. To address this need, embodiments described herein propose HiLITE, a hierarchical IL framework that maximizes energy efficiency while satisfying soft real-time constraints on embedded SoCs. This approach first trains DPM policies using IL; then, it applies a regression policy at runtime to minimize deadline misses. HiLITE improves the energy-delay product by 40% on average, and reduces deadline misses by up to 76%, compared to state-of-the-art approaches. In addition, the trained policies not only achieve high accuracy, but also have negligible prediction time overhead and small memory footprint.