Clock selection in a clock distribution network

Abstract

A clock selection circuit allows seamless switching between different clock signals in a clock distribution network. The clock selection circuit can be an Integrated Circuit (IC). The clock signals can be analyzed by a processor in communication with the IC to ensure the clock signals are validated. Analysis can include comparing time stamps between received pulses of the clock signals to determine if the clock signals are occurring at regular intervals. The processor can then assign a priority order to the clock signals and select one of the clock signals to use. An identifier associated with the selected clock signal can be programmed into the IC. The IC can then redistribute the selected clock signal to multiple other ICs in a hierarchical clock distribution network. Ultimately, the distributed clock signal can be received by server computers to ensure instances being executed have accurate and synchronized timing.