The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2025

Filed:

Jul. 03, 2024
Applicants:

Hefei Xinsheng Optoelectronics Technology Co., Ltd., Hefei, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Xiaoye Ma, Beijing, CN;

Yongxian Xie, Beijing, CN;

Hui Guo, Beijing, CN;

Jiale Li, Beijing, CN;

Zhiwei Ding, Beijing, CN;

Xiaowei Xu, Beijing, CN;

Huanhuan Huang, Beijing, CN;

Ling Liu, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); G06F 3/041 (2006.01); G06F 3/044 (2006.01); G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
G02F 1/13629 (2021.01); G02F 1/1368 (2013.01); G06F 3/0412 (2013.01); G06F 3/04164 (2019.05); G06F 3/0443 (2019.05); G09G 3/3614 (2013.01); G02F 2201/123 (2013.01); G06F 2203/04103 (2013.01); G09G 2300/0426 (2013.01); G09G 2320/0247 (2013.01); G09G 2320/0257 (2013.01); G09G 2330/023 (2013.01); G09G 2354/00 (2013.01);
Abstract

Disclosed are a display substrate, a display panel and a display device. The display substrate includes: a base substrate, multiple gate-line groups, multiple data lines, the multiple data line include: first type of data lines and second type of data lines alternately arranged along the first direction; multiple transistors, transistors in the same sub-transistor group are connected with the same gate line, transistors in adjacent sub-transistor groups are connected with different gate lines, and transistors of the same sub-transistor group are connected with different data lines; multiple pins, the multiple pins include: first type of pins and second type of pins alternately arranged along the first direction; two adjacent first type of data lines are connected with a same first type of pin, and adjacent second type of data lines are connected with a same second type of pin.


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