Transmitter for ultra-high speed and storage device including the same

Abstract

A transmitter includes a data generator, a serializer, a transmission driver and a feedback circuit. The data generator generates a retimed data signal and retimed test data by adjusting a delay amount of each of an input data signal and a test data based on adjusted clock signals. The serializer generates a serial data signal by serializing the retimed data signal based on multi-phase clock signals. The transmission driver generates an output data signal based on the serial data signal and transmits the output data signal through a channel. The feedback circuit detects the setup margin and the hold margin of the retimed test data through a separate path different from a path of the retimed data signal and generates the adjusted clock signals by adjusting delay amounts of the multi-phase clock signals based on the detected setup margin and hold margin of the retimed test data.