The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2025

Filed:

Feb. 25, 2020
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

You Qian, Singapore, SG;

Rakesh Kumar, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B06B 1/06 (2006.01); B81B 3/00 (2006.01); B81C 1/00 (2006.01);
U.S. Cl.
CPC ...
B06B 1/0666 (2013.01); B81B 3/0021 (2013.01); B81C 1/00246 (2013.01); B81B 2201/0271 (2013.01); B81B 2203/0127 (2013.01); B81B 2207/015 (2013.01); B81B 2207/07 (2013.01); B81C 2203/0735 (2013.01);
Abstract

A monolithic integrated device may include a first device having a complementary metal-oxide-semiconductor (CMOS) substrate, and a second device arranged over the CMOS substrate. The second device may include a first conductive element, and a second conductive element arranged over the first conductive element. A via opening may extend through the first conductive element and the second conductive element of the second device to an interconnect of the CMOS substrate. A via contact may be arranged in the via opening to contact the first conductive element, the second conductive element, and the interconnect of the CMOS substrate. The via contact electrically connects the first conductive element and the second conductive element of the second device to the interconnect of the CMOS substrate.


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