The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 10, 2025

Filed:

May. 10, 2021
Applicant:

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Pan Xu, Beijing, CN;

Zhidong Yuan, Beijing, CN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10K 59/124 (2023.01); H10K 50/81 (2023.01); H10K 50/844 (2023.01); H10K 59/179 (2023.01); H10K 71/00 (2023.01);
U.S. Cl.
CPC ...
H10K 59/124 (2023.02); H10K 50/81 (2023.02); H10K 50/844 (2023.02); H10K 71/00 (2023.02); H10K 59/179 (2023.02);
Abstract

A display substrate, a method of manufacturing a display substrate, and an electronic device are provided. The display substrate includes: a base substrate; a thin film transistor arranged on the base substrate; a first planarization layer arranged on a side of the thin film transistor away from the base substrate; a first protective layer arranged on a side of the first planarization layer away from the base substrate; a first conductive layer arranged on a side of the first protective layer away from the base substrate; and a second planarization layer arranged on a side of the first conductive layer away from the base substrate, wherein the display substrate is provided with a first via hole penetrating the first protective layer, and the first planarization layer is in contact with the second planarization layer through the first via hole.


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