The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 10, 2025

Filed:

Feb. 06, 2020
Applicant:

Lg Electronics Inc., Seoul, KR;

Inventors:

Hojung Lee, Seoul, KR;

Seung Yup Jang, Seoul, KR;

Jaemoo Kim, Seoul, KR;

Assignee:

LG ELECTRONICS INC., Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/00 (2025.01); H01L 21/04 (2006.01); H10D 12/01 (2025.01); H10D 62/17 (2025.01); H10D 62/832 (2025.01);
U.S. Cl.
CPC ...
H10D 84/146 (2025.01); H01L 21/0465 (2013.01); H10D 12/031 (2025.01); H10D 62/393 (2025.01); H10D 62/8325 (2025.01);
Abstract

The present disclosure relates to: a MOSFET device which is applicable to a semiconductor device and, particularly, is manufactured using silicon carbide; and a manufacturing method therefor. The present disclosure provides a metal-oxide-semiconductor field effect transistor device which may comprise: a drain electrode; a substrate disposed on the drain electrode; an N-type drift layer disposed on the substrate; a plurality of P-type well layer regions disposed on the drift layer and spaced apart from each other to define a channel; an N+ region disposed on the well layer regions and adjacent to the channel; a P+ region disposed at the other side of the channel; a gate oxide layer disposed on the drift layer; a gate layer disposed on the gate oxide layer; and a source electrode disposed on the gate layer.


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