The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 10, 2025
Filed:
Oct. 21, 2019
Applicant:
Northwestern University, Evanston, IL (US);
Inventor:
Jie Gu, Evanston, IL (US);
Assignee:
Northwestern University, Evanston, IL (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
A61F 2/72 (2006.01); A61B 5/00 (2006.01); G06F 18/214 (2023.01); G06F 18/25 (2023.01); G06N 3/047 (2023.01); G06N 3/063 (2023.01); G06N 3/08 (2023.01); G11C 11/54 (2006.01); H04W 4/38 (2018.01);
U.S. Cl.
CPC ...
H04W 4/38 (2018.02); A61B 5/486 (2013.01); A61F 2/72 (2013.01); G06F 18/214 (2023.01); G06F 18/251 (2023.01); G06N 3/047 (2023.01); G06N 3/063 (2013.01); G06N 3/08 (2013.01); G11C 11/54 (2013.01);
Abstract
Systems and/or methods may include an edge-computing distributed neural processor to effectively reduce the data traffic and physical wiring congestion. A local and global networking architecture may reduce traffic among multi-chips in edge computing. A mixed-signal feature extraction approach with assistance of neural network distortion recovery is also described to reduce the silicon area. High precision in signal features classification with a low bit processing circuitry may be achieved by compensating with a recursive stochastic rounding routine, and provide on-chip learning to re-classify the sensor signals.