The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 10, 2025

Filed:

Jul. 11, 2023
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Erik Santiago, La Tour du Crieu, FR;

Antoine Fabien Dubois, Austin, TX (US);

Pierre Philippe Calmes, Toulouse, FR;

Assignee:

NXP B.V., Eindhoven, NL;

Primary Examiner:
Int. Cl.
CPC ...
H02H 7/00 (2006.01); H02H 1/00 (2006.01); H02H 7/20 (2006.01);
U.S. Cl.
CPC ...
H02H 7/20 (2013.01); H02H 1/0007 (2013.01);
Abstract

One example discloses a power controller [] configured to modulate a load current sent to a load, including: a first chip [] including a set of higher-power circuits configured to directly modulate the load current sent to the load []; a second chip [] electrically coupled to the first chip and including a set of lower-power circuits; wherein the set of higher-power circuits are electrically isolated from the set of lower-power circuits; a power control path [] distributed between the first chip and the second chip, and configured to modulate the load current sent to the load; a diagnostics path [] distributed between the first chip and the second chip, and configured to monitor the higher-power circuits in the first chip and the lower-power circuits in the second chip for a set of fault conditions; wherein a portion of the diagnostics path in the second chip includes a plausibility circuit [] configured to compare a load current commanded by a first portion of the power control path in the second chip to the load current sent to the load by a second portion of the power control path in the first chip; and wherein the plausibility circuit is configured to transmit a safe-state request [] if the load current sent to the load is not equivalent to the load current commanded; and wherein the safe-state request is transmitted in parallel to the load current commanded by the first portion of the power control path in the second chip.


Find Patent Forward Citations

Santiago, Erik. (2025). Power controller (U.S. Patent No. 12327996). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12327996

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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