The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 10, 2025

Filed:

Dec. 07, 2021
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Nam Yeal Lee, Gyeonggi-do, KR;

Seung Won Lee, Gyeonggi-do, KR;

Dong Sub Kwak, Gyeonggi-do, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76816 (2013.01); H01L 21/76804 (2013.01); H01L 23/5226 (2013.01); H01L 21/31144 (2013.01); H01L 21/76843 (2013.01);
Abstract

A method for fabricating a semiconductor device includes: forming a dielectric layer over a substrate; forming a hole-shaped partial via in the dielectric layer; forming a line-shaped trench that partially overlaps with the partial via and has a greater line width than a line width of the partial via in the dielectric layer; forming a hole-shaped via that has a smaller line width than the line width of the partial via and penetrates the dielectric layer on a lower surface of the partial via; and gap-filling the via, the partial via and the trench with a conductive material, wherein a lower surface of the trench is positioned at a higher level than the lower surface of the partial via.


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