The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 10, 2025

Filed:

Sep. 01, 2021
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Ryota Hirai, Chigasaki Kanagawa, JP;

Daisuke Arizono, Yokohama Kanagawa, JP;

Yasuhiro Shiino, Fujisawa Kanagawa, JP;

Takuya Kusaka, Yokohama Kanagawa, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/08 (2006.01); G11C 16/04 (2006.01); G11C 16/12 (2006.01); G11C 16/26 (2006.01); G11C 16/30 (2006.01); G11C 16/32 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 16/349 (2013.01); G11C 16/0433 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/12 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 16/32 (2013.01); G11C 16/3404 (2013.01);
Abstract

A non-volatile memory of an embodiment includes: a memory cell array including a plurality of memory cell transistors; a plurality of word lines connected to a plurality of gates of the plurality of respective memory cell transistors; a VPGM monitor connected to at least one of the plurality of word lines; and a sequencer. When writing voltage is applied to a selected word line selected from among the plurality of word lines at data writing to the memory cell array, the sequencer detects voltage of the selected word line through the VPGM monitor and determines whether detected voltage obtained through the detection has reached a predetermined value.


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