Memory device and operating method of the memory device

Abstract

Embodiments of the present disclosure relate to a memory device, and an operating method of the memory device. The memory device includes a first memory block and a second memory block each including a plurality of memory cells. The memory device also includes a voltage generator for applying operating voltages to first global lines, selectively applying a positive voltage to global select lines included in second global lines while the operating voltages are applied, and applying a ground voltage to the other global lines except the global select lines among the second global lines. The memory device further includes a row decoder for turning on first pass switches between first local lines connected to the first memory block and the first global lines, and turning off second pass switches between second local lines connected to the second memory block and the second global lines.