The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 10, 2025

Filed:

Mar. 11, 2021
Applicant:

Polyn Technology Limited, London, GB;

Inventors:

Aleksandrs Timofejevs, Riga, LV;

Boris Maslov, Newport Beach, CA (US);

Nikolai Kovshov, Moscow, RU;

Dmitri Godovskiy, Moscow, RU;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/065 (2023.01); G06F 1/3206 (2019.01); G06F 1/3287 (2019.01); G06F 30/39 (2020.01); G06N 3/044 (2023.01); G06N 3/049 (2023.01); G06N 3/0499 (2023.01); G06N 3/063 (2023.01); G06N 3/082 (2023.01); G06N 5/04 (2023.01);
U.S. Cl.
CPC ...
G06N 3/065 (2023.01); G06F 1/3206 (2013.01); G06F 1/3287 (2013.01); G06F 30/39 (2020.01); G06N 3/044 (2023.01); G06N 3/049 (2013.01); G06N 3/0499 (2023.01); G06N 3/063 (2013.01); G06N 3/082 (2013.01); G06N 5/04 (2013.01);
Abstract

Systems and methods are provided for analog hardware realization of neural networks. The method includes obtaining a neural network topology and weights of a trained neural network. The method also includes transforming the neural network topology to an equivalent analog network of analog components including operational amplifiers and resistors. Each operational amplifier represents an analog neuron of the equivalent analog network, and each resistor represents a connection between two analog neurons. The method also includes computing a weight matrix based on the weights of the trained neural network. The method also includes generating a resistance matrix for the weight matrix. The method also includes pruning the equivalent analog network to reduce the number of operational amplifiers or the resistors, based on the resistance matrix, to obtain an optimized analog network of analog components.


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